The present invention relates to a bipolar transistor with a reduced collector series resistance and a method for fabricating the same.
In conventional fabrication methods for the bipolar transistors, a burying layer is formed on a semiconductor substrate and an epitaxial layer is grown on the burying layer. In order to shorten these conventional fabrication processes for the bipolar transistors, it was, however, proposed to form an n-type highly doped diffusion layer by an ion-implantation at a high energy in the range of 1 MeV to 2 MeV. In this method, an n-type burying layer and an n-type well layer overlying the n-type burying layer may be formed by use of the same mask but at different ion-implantation energies. This may shorten the fabrication processes for the bipolar transistors. This method for fabricating the bipolar transistor will be described with reference to FIGS. 1A and 1B.
FIG. 1A is a cross sectional elevation view illustrative of the conventional bipolar transistor wherein the n-type burying layer and the n-well layer overlaying the n-type burying layer have been formed by ion-implantation at different energies by use of the same mask.
FIG. 1B is a plane view illustrative of the conventional bipolar transistor illustrated in FIG. 1A.
The bipolar transistor is formed on a p-type semiconductor substrate 201. Trench isolations 209 are formed within trench grooves 207 formed in the p-type semiconductor substrate 201 so that the bipolar transistor is formed in a region surrounded by the trench isolations 209. An n.sup.+ burying layer 210 is formed in the p-type semiconductor substrate surrounded by the trench isolations 209 by an ion-implantation of n-type impurity at a high ion-implantation energy. An n-well region 211 is then formed, which overlies the n.sup.+ burying layer 210 by a subsequent ion-implantation of n-type impurity at an ion-implantation energy lower than the ion-implantation energy used for forming the n.sup.+ burying layer 210. Field oxide films are selectively formed on a surface of the substrate A p-type intrinsic base region 221 is formed in an upper region of the n-well region 211. A collector diffusion layer 227 is selectively formed in an upper portion of the n-well region 211. The collector comprises the n.sup.+ burying layer 210, the n-well region 211, and the collector diffusion layer 227.
Graft base regions 234 are formed to surround the intrinsic base region 221. Base plug electrodes 232 are formed, which are in contact with the graft base regions 234. An emitter region 233 is formed in an upper portion of the intrinsic base region 221 to form a vertical n-p-n structure. The emitter region 233 may be formed by diffusion of an n-type impurity from an emitter plug electrode 229 into the intrinsic base region 221. Electrode interconnections 237 are formed in contact holes to be made into contact with the base plug electrodes 232, the emitter plug electrode 229 and the collector diffusion layer 227.
In the above bipolar transistor, a current flows downwardly from the collector diffusion layer 227 through the n-well region 211 to the n.sup.+ burying layer 210 and then flows laterally through the n.sup.+ burying layer 210 for subsequent flowing upwardly from the n-well region 211 to the intrinsic base region 221. When the bipolar transistor is placed in an active state, a space charge region extends under the intrinsic base region 221 and over the n.sup.+ burying layer 210. Namely, the intrinsic base region 221 is connected through the space charge region to the n.sup.+ burying layer 210. The space charge region is extremely lower in effective resistivity to current than the n-well region 211. Further, since the n.sup.+ burying layer 210 is higher in impurity concentration than the n-well region 211, the n.sup.+ burying layer 210 is much lower in effective resistivity to current than the n-well region 211. Current tends to flow through a region having a lower resistivity than other region surrounding the region, for which reason the current flows in a current path which extends through the n-well region 211 as short as possible but through the n.sup.+ burying layer 210 as long as possible. As a result, the current path extends downwardly from the collector diffusion region 227 through the n-well region 211 to the n.sup.+ burying layer 210 and further extends laterally through the n.sup.+ burying layer 210 and moreover extends upwardly from the n.sup.+ burying layer 210 through the space charge reign to the intrinsic base region 221. In the current path described above, the space charge region and the n.sup.+ burying layer 210 are much lower in effective resistivity to current than the n-well region, for which reason an effective collector series resistance is defined mostly by the resistance of the n-well region 211 under the collector diffusion region 227. Since the thickness of the n-well region 211 is determined in consideration of a base-collector withstand voltage, it is unlikely that the thickness of the n-well region 211 can be reduced. The collector series resistance of the above bipolar transistor is, therefore, substantially defined by the resistance of the n-well region 211 when the current flows from the collector diffusion region 227 to the n.sup.+ burying layer 210 downwardly. As described above, the resistivity is defined by the impurity concentration. The n.sup.+ burying layer 210 has a high impurity concentration in the order of 1.times.10.sup.19 atoms/cm.sup.3, whilst the n-well region 211 has a lower impurity concentration in the order of 1.times.10.sup.13 atoms/cm.sup.3. If, in order to reduce the resistivity of the n-well region 211, the impurity concentration of the n-well region 211 is increased, then this raises problems with crystal defects caused by crystal damages in ion-implantation at high dose. Remarkable crystal defects cause leakage of current between collector and base or between emitter and collector.
In the above circumstances, it was practically difficult to reduce the collector series resistance to less than 100 .OMEGA.. If the collector series resistance is not sufficiently reduced and the bipolar transistor is made to operate in a large collector current region, then the bipolar transistor is likely to be saturated or its cut off frequency lowered, thereby the required good properties can not be obtained.
In order to settle the above problems with a high collector series resistance, there was proposed another bipolar transistor with a lateral n-p-n structure in place of the above vertical n-p-n structure. A typical one of the conventional lateral n-p-n structure bipolar transistors will be described with reference to FIGS. 2A and 2B. This conventional lateral n-p-n structure bipolar transistor is disclosed in the Japanese laid-open patent publication No. 64-15973.
FIG. 2A is a cross sectional elevation view illustrative of the conventional bipolar transistor wherein a highly doped n-type collector diffusion layer laterally surrounds an n-type epitaxial layer which surrounds an intrinsic base region so that a collector plug electrode is connected via the n-type highly doped collector diffusion layer to a highly doped n-type burying layer whereby currents flow from the collector plug electrode through the n-type highly doped collector diffusion layer to the highly doped n-type burying layer.
FIG. 2B is a plane view illustrative of the conventional bipolar transistor illustrated in FIG. 2A.
On a p-type semiconductor substrate 301, field oxide films 304 are selectively formed to define an active region on which a bipolar transistor is formed. A highly doped n-type collector diffusion layer 306 is formed to laterally surround an n-type epitaxial layer 303 which surrounds an intrinsic base region 307. A ring-shaped emitter region 309 is formed in an upper portion of the intrinsic base region 307. A collector plug electrode 305 is formed in contact with the n-type highly doped collector diffusion layer 306. An n.sup.+ burying layer 302 is formed under the intrinsic base region 307 and under the n-type highly doped collector diffusion layer 306 so that the collector plug electrode 305 is connected via the n-type highly doped collector diffusion layer 306 to the n.sup.+ burying layer 302. Currents flow from the collector plug electrode 305 through the n-type highly doped collector diffusion layer 306 to the n.sup.+ burying layer 302. The currents then laterally flow through the n.sup.+ burying layer 302 and thereafter upwardly flow through a space charge region formed under the intrinsic base region 307 to the intrinsic base region 307, wherein the space charge region is formed only when the bipolar transistor is in active state. The current path comprises the n-type highly doped collector diffusion layer 306, the n.sup.+ burying layer 302 and the space charge region under the intrinsic base region 307. Namely, the current path is free of a highly resistive region, for which reason the collector series resistance of the bipolar transistor illustrated in FIGS. 2A and 2B is lower as compared to that illustrated in FIGS. 1A and 1B. The bipolar transistor illustrated in FIGS. 2A and 2B, however, is difficult limitation to lateral scale down due to the following reasons.
The n-type highly doped collector diffusion layer 306 is formed by a diffusion of n-type impurity from the collector plug electrode 305 into the n-type epitaxial layer 303. The diffusion is continued until the impurity reaches the top of the n.sup.+ burying layer 302 whereby the collector plug electrode 305 is connected via the n-type highly doped collector diffusion layer 306 to the n.sup.+ burying layer 302. Since the impurity diffusion is isotropic, there is both vertical diffusion and lateral diffusion. In consideration of the structure of the bipolar transistor, it is required that the n-type highly doped collector diffusion layer 306 is separated by the n-type epitaxial layer 303 from the intrinsic base region 307. Notwithstanding, the lateral diffusion of impurity from the collector plug electrode 305 forms the n-type highly doped collector diffusion layer 306 which laterally extends from the collector plug electrode 305 toward the intrinsic base region 307. Accordingly, it is essential that the collector plug electrode 305 is spaced in a lateral direction from the intrinsic base region 307 by a distance larger than a lateral diffusion distance. This provides a limitation to the lateral scaling down of the bipolar transistor. The above diffusion process may also limit increases in impurity concentration of the collector diffusion layer 306. Namely, it is difficult to cause the collector diffusion layer 306 to possess an impurity concentration as high as the n.sup.+ burying layer 302. This limitation to the increase in the impurity concentration of the collector diffusion layer 306 results in a limitation to a reduction in collector series resistance of the bipolar transistor.
In the above circumstances, it had been required to develop an improved bipolar transistor having a substantially reduced collector series resistance and also having a structure suitable for a substantial space down in lateral directions.